Wow, that’s a depressing read. Appeals to authority, proof by assertion, and refusal to share any experimental methodology that backs up the assertions. That issue tracker is in dire need of more active moderation.
This puts the chip designer in a bind: if an instruction calls for v0 to be used as a vector input, then the low-order bits of v0 would want to be stored near the low lanes. But if an instruction calls for v0 to be used as the mask, suddenly those same bits want to spread across all the lanes! The ISA basically wants the designer to have the same bit in two different places at once.
And, although I’m not knowledgeable enough about chip design to know what the best work-around is here, that’s basically what they’re going to have to do. I’d imagine most high-performance designs will resort to some kind of shadowing where they try to keep the bits stored as if they were a mask register when they come out of mask instructions, as if they were a vector register when they come out of vector instructions, and then have some hacks in there to work around cases where the instruction stream does something unexpected and the bits aren’t in the right place.
Yeah, I don’t really think it is a big deal to have a shadow register for v0 to be used as a mask register. In the general case, the actual implementation of a CPU looks wildly different than what you might think just looking at the programming model.
I think the github issue linked by /u/mordae covers the concerns of the OP fairly well.
I’ll wait until we hear from some chip designers as to whether the current RVV v1.0 design is actually a problem or not.
I’m certainly no computer architecture expert, but I also don’t see how it as a major concern. It doesn’t seem any worse than having a carry flag that is used as both an output from high-order bits and as an input for low-order bits. Or any worse than element re-ordering in packed SIMD. Yes, there will be wires crossing lanes. That’s quite common, though.
The Github issue is a pretty good read, thanks for sharing!
Wow, that’s a depressing read. Appeals to authority, proof by assertion, and refusal to share any experimental methodology that backs up the assertions. That issue tracker is in dire need of more active moderation.
Yeah, I don’t really think it is a big deal to have a shadow register for v0 to be used as a mask register. In the general case, the actual implementation of a CPU looks wildly different than what you might think just looking at the programming model.
I think the github issue linked by /u/mordae covers the concerns of the OP fairly well.
I’ll wait until we hear from some chip designers as to whether the current RVV v1.0 design is actually a problem or not.
I’m certainly no computer architecture expert, but I also don’t see how it as a major concern. It doesn’t seem any worse than having a carry flag that is used as both an output from high-order bits and as an input for low-order bits. Or any worse than element re-ordering in packed SIMD. Yes, there will be wires crossing lanes. That’s quite common, though.