It was one of the ideas I had for Raspberry Pi 3. I keep thinking about buying one. They say it’s best even if less hardware since so much software already works on it. Helps newcomers out. I want an always-on box that doesn’t use much power.
Oberon port, either Oberon or A2 Bluebottle, was one of my ideas. I also thought about porting it to Rust then backporting it to Oberon. Basically, knocking out any temporal errors plus letting it run without GC. Then, Oberon-to-C-to-LLVM for performance boost. Oberon in overdrive. ;)
If you wait 15 years on your project, then Wirth’s habits might mean there will be another 5-10 Oberon’s released with minor, feature changes before you get started. He might try dropping if statements or something. Who knows.
Confusingly, RISC5 isn’t related at all to RISC-V as far as I know, it’s just the sixth iteration of a series of designs with features that are introduced incrementally for pedagogical purposes, numbered RISC-0 through RISC-5. The series is described in this document (PDF); look towards the end of the first page for the section starting with “The development of our RISC progresses through several stages.”
The whole source and the book explaining the stuff is at https://projectoberon.com
In my Copious Free Time (read: after my kids are in college, so ~15 years from now) I’d like to port Oberon to the Raspberry Pi. It would be fun.
It was one of the ideas I had for Raspberry Pi 3. I keep thinking about buying one. They say it’s best even if less hardware since so much software already works on it. Helps newcomers out. I want an always-on box that doesn’t use much power.
Oberon port, either Oberon or A2 Bluebottle, was one of my ideas. I also thought about porting it to Rust then backporting it to Oberon. Basically, knocking out any temporal errors plus letting it run without GC. Then, Oberon-to-C-to-LLVM for performance boost. Oberon in overdrive. ;)
If you wait 15 years on your project, then Wirth’s habits might mean there will be another 5-10 Oberon’s released with minor, feature changes before you get started. He might try dropping if statements or something. Who knows.
Well actually I would remove the FOR loop given it’s just syntactic sugar for a WHILE.
However for some reason it seems that Wirth likes it. :-)
Anyway… Wirth is a light source in these dark days: he will always remind us that less features mean less bugs.
I just noticed this was a new submission. So, I’ll add OberonStation here, too.
Any idea why he called the processor module “RISC5”? Is this just a mere nod to RISC-V, or is there some deeper connection?
Confusingly, RISC5 isn’t related at all to RISC-V as far as I know, it’s just the sixth iteration of a series of designs with features that are introduced incrementally for pedagogical purposes, numbered RISC-0 through RISC-5. The series is described in this document (PDF); look towards the end of the first page for the section starting with “The development of our RISC progresses through several stages.”