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    I am excited about this project!

    At first glance it appears to be an easy way to describe what I want an FPGA to do, and produce a design that’s easily integrated into other software I’m building.

    I’ve tried and failed to learn enough Verilog to build my own FPGA designs. My ‘sentinel’ question has always been “When FPGAs can be used to accelerate their own synthesis, FPGAs have reached usefulness”. This might be the thing I want!

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      When FPGAs can be used to accelerate their own synthesis, FPGAs have reached usefulness

      This reminds me of Wirth, who had a similar mindset on compiler optimizations…

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        I’ve been playing with nmigen and I want to give this a try too.