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    I wish work like this would gain more traction. From my experience, working directly with VHDL (and FPGAs) the proprietary software is just too cumbersome to use. I would much rather use an opensource/libre toolchain because it feels more modularized and leaves the option to create a personal workflow, just like the author described. It appears that this will take quite some time, but I am really happy that work in that direction is being done!

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      I agree, that’s why I started learning FPGAs when yosys became a thing. The whole suite of tools is really active the past year or so. There are now two place and route tools, more models and vendors gaining support, it’s growing fast!

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        I haven’t had much experience with yosys, the last time I heard about it was more than a year ago, but I’m glad that it seems to have improved so much. Currently I’m only using FPGAs for machine learning, but the code is fortunately generated automatically so I don’t need to touch it myself.