Exciting to see ARM finally coming to fruition, it’s a shame there is no actual hardware in the review.
Nice, but what i’d really like to see is RISC V
80 ARM cores. Glorious. But I don’t see any numbers on what happens when the L1/L2 cache cannot satisfy a read — with that many cores, the memory buses must be heavily loaded. Will the penalty for random RAM access be even worse than for other modern CPUs?
It appears this design is cache-starved indeed, probably for manufacturing reasons.
It may be a great design for applications with a small working set — ones that can busy all the cores with the same code. Not exactly SIMD, more “same few million instructions, many different data”.