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    Huh – slightly surprised to see it uses the higher-overhead 8b/10b instead of something denser like 128b/130b as employed in PCIe 3+. (And also that USB2 apparently has nothing of the sort at all, though I guess I don’t have much gut sense of the point at which those measures become necessary.)

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      Wouldn’t 8b10b provide a lot more frequent transitions between 1 and 0 than 128b130b? Maybe USB wants high enough clock variance tolerances that it needs to guarantee transitions more frequently than 128b130b would?

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        USB1.1 and USB2 use bit stuffing. https://www.embedded.com/bit-stuffing/

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          I’d assume that the tolerances are way lower in PCIe (i. e. it doesn’t have to worry about people moving and bending cables while operating).