1. 45
  1.  

  2. 39
    1. 10

      The changes in question: amd and intel.

      1. 6

        Wow is this complex. Both the current IDT stuff, and the FRED draft, all of it. Stack levels that Intel emphasizes are not the same as rings… what is all of this stuff? Who ever asked the CPU to put crap on the stack by itself?

        ARMv8 just jumps to (value of an MSR) + (offset depending on exception type). That’s it, that’s all you need to know other than understanding what these types even are. Beautiful.

        1. 6

          I was thinking “huh, x86_64 can’t be that much of an outlier”; considering that the first thing one wants to do in an interrupt handler is usually dumping all the registers somewhere anyway, I thought this would be typical. So I did a little research among its contemporaries. 32 bit ARM indeed just jumps to a particular address and executes what’s there, which will presumably be a jump instruction to the real instruction handler, and AArch64 does the same thing. Not too surprising, but as far as I can tell MIPS32 is similarly simple, and PowerPC is kinda weird in its own way since its interrupt table contains 256 bytes of code per interrupt that is executed on its own, but still seems simpler than x86. VAX has a special stack for interrupts but I think only stores the program counter and (I think) current stack register on it, 68k is similar, while Alpha has a much more complicated interrupt mechanism that dumps various registers onto various stacks and loads new ones depending on the type of exception.

          So, there’s a whole gamut, and x86 is on the far edge of the fancier side. Interrupts in general are complicated, and ARM is a bit of an outlier in how simple it is. It’s pretty nice, I have to say.

          1. 2

            PowerPC is kinda weird in its own way since its interrupt table contains 256 bytes of code per interrupt that is executed on its own

            That sounds very similar to what ARM does? ARM also calls this area “interrupt vector”, it’s also a bunch of fixed-size sections of code per interrupt type, but that’s exactly what “jumping to a fixed address + offset based on type” is. Though you didn’t say per interrupt type, that’s the only difference I can see.

          2. 1

            ARMv8 just jumps to (value of an MSR) + (offset depending on exception type). That’s it, that’s all you need to know other than understanding what these types even are. Beautiful.

            Same way m68k does it.

            It is sad that there are so many “modern architectures” that don’t even get basic vectored interrupts and exceptions.