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    The VAX-11 is one recent computer that provides support for queue data structures.

    Now immortalized in posix: http://pubs.opengroup.org/onlinepubs/009695399/functions/insque.html

    And then system designers had a change of heart and decided that hard coding data structures into the processor wasn’t cool anymore.

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      Relevant - Unisys (the company that owns and has been working on converging the IP of the Burroughs Large Systems and UNIVAC hardware lines, and the MCP and OS2200 operating systems, respectively, and whom actively markets and maintains these platforms) has made available FREE (well, licensed, but, free as in beer) releases of the current software as well as the virtual machines software necessary to run them on commodity hardware.

      If you’d like to be able to experiment hands on with these platforms, check out https://lobste.rs/s/r5wino/clearpath_mcp_express which I previously posted.

      For many of us, this was a long-awaited development from Unisys, coming as a quite a surprise after many years of seemingly futile requests for some sort of hobbyist program.

      This is a great way for mainframe hobbyists, enthusiasts, students, and others who are just curious to gain experience with these platforms.

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        It’s fascinating to read about some of the classical architectures that are quite different from the ones we mostly use today. This caught my eye…

        Machines worth keeping an eye on are the iAPX-432

        … and reminded me of a blog post (by @bcantrill) about the 432 from almost a decade ago, which refers to a paper about the 432 from ~1988.

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          They fixed a lot of it with i960. Just the RISC + object additions + high availability would make an interesting CPU for high-assurance systems. It ended up in the F-35. The modern take on capability-secure CPU’s with intent for practical adoption is Cambridge’s CHERI which runs FreeBSD already. Best interim project, aside from peer reviewing and pentesting their scheme, is to replace the MIPS CPU in there with a flexible RISC-V core for an ASIC. Then, with a UNIX protected at CPU level, there will be many fewer attacks to mitigate with main problem being a performance hit. Then, we can just go back to throwing hardware at our problems. :)

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          I already mentioned CHERI. The closest thing to Burroughs CPU aside from safe C’s (eg Hardbound or Watchdog architecture) or Java CPU’s (esp JOP or Sandia SSP) would be the SAFE architecture. There was one company wanting to make a brand of secure CPU’s combining it with RISC-V. I’m not sure if they will. I did like the earliest version had two things: basic, ultra-fast checks for most primitive ops like arrays and pointers; more complex checks for rest. Final architecture used some metadata engine for flexible policies so one component could do everything. It looked pretty simple, too. So, maybe checking primitives is better or maybe their flexible mechanism is better. Who knows.

          One cool thing about SAFE’s flexibility is that it supported tons of policies that could be useful for many types of analysis where you can just run spec-based or random testing at hardware speed with CPU-level exceptions taking you right to the problem. You might have a policy for memory safety, one for covert channels, one for concurrency bugs maybe, and so on. Maybe a whole cluster with nodes running arbitrary policies for piles of test cases. Like ARM setups, both SAFE and CHERI have relatively small additions to hardware that’s already many times smaller than x86. So, you get plenty of cores on the cheap once upfront investment is paid off.