Abstract: “Although FPGAs continue to grow in capacity, FPGA-based soft processors have grown very little becauseof the difficulty of achieving higher performance in exchange for area. Superscalar out-of-order processor microarchitectures have been used successfully for hard processors for many years, and promise large performance gains if they can also be used for FPGA soft processors. Out-of-order soft processor microarchitectures have so far been avoided due to the area increase and the expectation that a loss in clock frequency would more than offset the instructions-per-cycle (IPC) gains.

This thesis presents the design of the microarchitecture and circuits of a two-issue (superscalar) outof-order x86 FPGA soft processor. Our microarchitecture achieves 2.7 times the per-clock performance of a performance-tuned Nios II/f, Altera’s fastest (RISC-like, single-issue, pipelined) soft processor, and 0.8 times the frequency, for a total performance improvement of 2.2 times. The processor is projected to use around 28 700 Stratix IV Adaptive Logic Modules (ALMs), which is 6.5 times the area of the Nios II/f, but still only a small fraction of a modern FPGA.

In addition to performance improvements, our microarchitecture design is sufficiently complete and correct to boot most 32-bit x86 operating systems unmodified. We also design circuits for most of the components in the processor. These highly-optimized circuits are key to achieving high operating frequency despite the increased complexity of out-of-order execution. Through the design of our processor, we demonstrate that a high-performance processor microarchitecture can be implemented successfully on FPGAs. Beyond the proposed microarchitecture, the processor circuits presented in this thesis will enable new out-of-order soft processor microarchitectures of varying performance, cost, and instruction set, created from variations of our circuits.”

(emphasis added in bold on key point)