I found this StackExchange answer while researching the SPARC ISA after nickpsecurity mentioned it. Very interesting!
The European Space Agency needed better computers for their missions, and decided to choose a fully-open RISC ISA. SPARC was chosen because it was the only existing ISA which fit the bill. Designing their own ISA would have required reimplementing or porting a compiler and OS toolchain.
LEON/Gaisler processors are completely open designs (VHDL is available), although they are only 32-bit SPARC processors. They are relatively weak computers, but apparently suitable for space, as they are fault tolerant / radiation hardened!
Glad it led you to something. Gaisler was kind enough to open-source his Leon3 work here:
http://www.gaisler.com/index.php/products/processors/leon3
The SPARC ISA had been open for some time under OpenSPARC foundation. They used OpenFirmware standard, too. Everything you want to know about your system is available. They only required a registration fee to use the trademark with none of the licenses and royalties of ARM, MIPS, x86, POWER, etc. That’s why I found it ridiculous that there were all kinds of projects talking open-hardware but nobody would build on the only GPL SOC. Even better, it’s designed where you can use automated tools to customize it to have just the features you want. Then easily integrate custom stuff like SAFE and CHERI do for enhanced security. Several academics used Leon for this reason. Oracle’s OpenSPARC T1 and T2 CPU’s were also GPL’d with some teams using them.
http://www.oracle.com/technetwork/systems/opensparc/index.html
I still suggest reviewing and throwing those suckers onto an ASIC. Then, we have high-performance CPU’s without issues of Intel, AMD, or IBM. Replace decoders and stuff with RISC-V’s to cheat your way to high-performance version of it. Still languishes with FOSS community mostly ignoring Leon and T1/T2. Raptor also wants to pay a huge licensing fee to use “Open"POWER instead of do OpenSPARC T2 for free. SAFE project used dead Alpha ISA, Cambridge CHERI used patent-locked MIPS, and Chinese used both in ShinWei and Loongson. Only Jap’s and Russians built on it industrially that I’m aware. (sighs) Least what Oracle and Fujitsu are doing with it shows it was a good recommendation years ago. Those CPU’s kick ass!
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Not to mention the threat of Oracle suing you, regardless of the GPL. Java is GPL’d, and look what happened to Google.
That’s somewhat disingenuous, because Google wasn’t attempting to comply with the GPL either.
I understand that risk. Mentioned it in other posts. Main recommendation was turning Leons into 64-bit multicores. However, I thought Oracle’s main suits were over non-GPL stuff left in Java. It was a hybrid of OSS and proprietary stuff. Then there’s was an API issue.
In any case, all the OpenSPARC artifacts are released under open-source license for anyone to use per their own website. That seems easy to defend in court vs stuff like Java. Especially quoting their own FAQ’s in licensing that make it clear you can use it anyway you want so long as you GPL the result:
http://www.oracle.com/technetwork/systems/opensparc/opensparc-faq-1444660.html
Last ditch possibility if there’s still patent claims is to get a patent license from Oracle. This would probably be paid as with the other ISA licenses. The difference is you get an extremely open result vs others that’s also high-performance. I’d say keep the software on it cross-platform just in case, though. ;)
“extremely few people are willing to give up “modern performance” for security.”
That’s correct. An unwillingness to make sacrifices is main reason for insecurity and closed platforms everywhere. Can’t help such people unless biggest suppliers just decide to be benevolent.
“but i doubt it would be enough. not even if you were willing to pay the $$$ to get it laid out and fabbed on modern processes.”
It would have to be 45nm or lower to get decent performance with standard cell. The initial development would cost money. From there, the cost is spread across the masks, wafers, and packaging with volume reducing it.
“you’re going to have to engage in serious architectural innovation, and that’s not SPARC. :(”
Possible but still open to debate. The ARM people hardly put anything in their designs. Just kept them lean and on newer nodes. Being used for all kinds of desktop replacements. Cavium squeezed a bunch of MIPS cores with some common accelerators to get results. Similar techniques might work for the various SPARC I.P.. At least the academics in the RISC-V community are experimenting with high-performance designs. We might get lucky where the architecturally better ones are open-sourced to some degree.
Mildly tangental: Is anyone aware of where you can buy SPARC development hardware?
Searching for “LEON development board” turned up a few hits. Here is one I found: http://www.pender.ch/products.shtml
The standalone board they offer is €850 and relatively weak, but it does come with FPGA, and radiation fault-tolerance.
We have been using Terasic kits. (I think they are cheaper) http://www.terasic.com.tw/en/
(Odds on you don’t need the radiation fault tolerance)
CHERI team uses Terasic, too.
One of my early suggestions was to do a Pi- or Arduino-like design with either Leon3 or Leon3FT running open firmware and Linux. Keep it cheap. That way tinkerers could develop on the platform. Nobody did. Pulpino or whatever might do it for RISC-V on 28nm, though. Those were being prototyped last I checked.
Oops, I looked at this further in-depth and the board does not include a physical LEON CPU, nor is it rad-hardened. They are simply FPGA boards “developed for LEON development”.
No, they’re a mix of FPGA and CPU boards. See here:
http://www.gaisler.com/index.php/products/boards
Notice the GR712RC is a Leon3 CPU and CR740 is Leon4. Both fault-tolerant models. So, these are likely the boards space applications get either developed on or final testing on. Most of rest look like FPGA’s.
Ah yeah, the “CPCI” ones have real Leon CPUs, but the standalone GR-XC6S board is described by gaisler.com as a “low-cost Spartan6 FPGA Development board”.
Sparc dev hardware? Or Leon devkits?
Any Altera Cyclone 3 and up (and probably Xilinx) dev kits probably can run a Leon core.