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    Hi Dan – thank you for archiving this information. As someone who’s starting to get interested in computer architecture, it’s been hard trying to find thorough informational posts on ARM/x86 and RISC/CISC, outside of reading a textbook.

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      L4 [IBM System/3x0] happens to be one in which you can tell the length of the instruction from the first few bits, has a fairly regular instruction decode, has relatively few addressing modes, no indirect addressing. In fact, a big subset of its instructions are actually fairly RISC-like, although another subset is very CISCy.

      IIRC, it might be because of the Model 44, which had a simplified decoder (limited instruction forms, less direct-memory) in exchange for greater integer performance - arguably a kind of ur-RISC.

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        Ah, from the days when we believed in sufficiently smart compilers. :)

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          Putting our trust in sufficiently smart processors hasn’t exactly gone well either to be fair.

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            I think the bigger issue here is that software is usually compiled once per ISA and not per processor, so the compiler never gets the chance to be very smart.

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