1. 3

See also: https://www.phoronix.com/scan.php?page=article&item=intel-jcc-microcode (with benchmarks)


  2. 1

    Summary, if I understand this correclty: For some Intel CPUs, conditional jump instructions ending at or crossing cache line boundaries can lead to unpredictable behavior. To fix this, Intel released microcode updates that detect such cases and disable caching for those situations. This impacts performance. To “fix” this, Intel has released patches for GNU Assembler to insert mitigations.