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    I hope Fabien puts this in formation here: https://en.wikipedia.org/wiki/USB

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      one question that just occurred to me looking this table: why does USB (universal serial bus) have multiple RX and TX lines?

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        I am not an expert, but… well, depends on what you mean.

        If you’re looking at the 8 wire cable, USB uses differential signalling, so instead of a bit being a + or - voltage over one wire compared to the ground (the way RS-232 does for example), a bit is represented as a + voltage on one wire and a - voltage on another wire. So, you need two signal wires as well as the ground, hence RX+ , RX- , and TX+ , TX-. Differential signaling is nice because it makes the electromagnetic fields around each wire mostly cancel each other out, which means less interference and faster signal rates.

        If you’re looking at the 16 wire cable, well, we have RX1+, RX1-, RX2-, RX2+, TX1+, TX1-, TX2-, TX2+. That website describes this as “2 lanes”, so I’m going to go out on a limb here and guess that those two lanes can both move data at the same time but are otherwise basically independent of each other. So each single lane is still serial, it transmits and receives 1 bit at a time, you just have more of them at once. (PCIe works this way too, IIUC.) If it was a parallel bus then instead of two independent serial lanes then the RX and TX lines would be electrically linked together, so TX1 and TX2 could not operate independently, you always had to transmit data in 2-bit chunks. This means that the signal in TX1 and TX2 would have to start and stop precisely at the same time, while each serial lane operates on its own clock. This is very much a guess though.

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          The numbered TX/RX pairs are also used alternately to implement the reversible nature of the USB-C plug - the device at the other end may not have both lanes connected. (e.g. USB C-to-A or C-to-B cable)

          I don’t know how simultaneous use for Gen 2x2 (and the other variants which are much rarer in practice) works in detail at the electrical level, but from the logical protocol level, the two lanes are invisible. Transfers are simply faster, as far as I can tell. So presumably data must be fairly tightly interleaved. But I suppose this is the way it works for PCIe too.

          Speaking of PCIe, Gen 2x2 mode is still fairly rare (Intel has only just integrated it into their very latest set of processors, AMD and Apple haven’t implemented it, and I think there’s a host controller from Asmedia) so one of the main uses for the 2 sets of differential lines right now are alternate modes: PCIe (Thunderbolt) and DisplayPort.

          Finally, nobody’s mentioned D+ & D- yet. These are also data lines, but bi-directional. They’re for the high-, full-, and low-speed devices, which essentially form an entirely separate bus. (Although I think it still plays a role during enumeration of superspeed devices.)

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          In addition to icefox’s answer, there’s a great Ben Eater video about this (because of course there is): https://youtu.be/wdgULBpRoXk

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            Thank you! I love Ben’s videos, and somehow managed to miss this one