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For background on lowRISC, our goal is to produce a fully open-source System-on-Chip in volume, using the RISC-V instruction set architecture. See our about page for more details. Feel free to ask questions in the comments.

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    Hey, that’s awesome. I’m on the RISC-V team at Berkeley, and we’re trying to move towards un-tethered systems as well. I won’t be able to attend the RISC-V workshop, but some of the other students will. I think it would be great if you could share some of your experience with them so we know what pitfalls to avoid.

    So far, we have most of the required hardware features like MMIO and a hardware device tree implemented. From here on, it’s mostly implementing peripherals and updating all the software.

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      It’s a shame you can’t make it. Both Wei Song and I are flying over for the workshop and presenting - Wei will give more detail on the untethering work. It will be good to catch up with your colleagues.

      Our current implementation uses a separate I/O bus for simplicity and to minimise the invasive changes to the Rocket codebase. It seems like your MMIO implementation may have sorted most of the bugs now, so we may want to move over to that.

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      Nice! Any insight into lowRISC vesus the work that the Open Proscessor Foundation is doing with J2/SuperH?

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        Sure. First of all, the focus of OPF right now is on much smaller core designs (microcontroller class) while we’re heading towards a SoC that can “run Linux well”. They’re releasing new designs as the original SH patents expire. My understanding is it won’t gain a MMU (memory management unit) until 2017 with 64-bit support coming sometime after that. Instead, we are using the open RISC-V ISA and basing our application cores on the Rocket design out of Berkeley. The upside is you get a clean, modern ISA that anyone can use right now. The downside is there’s a fair bit of work still to be done on the software side - but there is already a Linux port, decent GCC toolchain etc. Aside from producing RTL for a complete SoC reference design, we also intend to produce the SoC in volume and sell low-cost development boards. In the future, it would be great to be able to offer a regular (e.g. every 18-24 months) tapeout schedule, so people know they’ll be able to see their contributions in silicon in a reasonable timeframe.

        In summary: we’re both interested in pushing forward open hardware, but are going about it different ways and have a different focus for the time being. I’m very interested in their DSP design http://0pf.org/working-groups.html.

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        That’s great news, I really hope RISC-V and lowRISC projects will be successful. I know this is premature, but taking the opportunity to ask when can we expect dev boards to reach general availability?

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          Thanks for the words of support. We intend to tape out a test chip next year, and we’d get ~100 dies through a multi-project wafer (possibly more if there’s spare space on the wafer and the fab is being nice to us, or if we pay for extra wafers). This would produce some dev boards for key contributors and project partners. Assuming a successful test chip, I’d expect general availability to follow in 2017.