Aside: I don’t know how much time regalloc takes compared to optimisation, linking, etc. but I wonder if there’s a noticeable difference in effort between x86_64 (where there are 16? registers, some with fixed purposes) and RISC-V (which has 32 registers with no fixed purpose, modulo ABI and compressed instructions).
For more on register allocation design, I thought this article was really good: Cranelift, Part 4: A New Register Allocator (regalloc2).
I notice there’s now a regalloc3 as well, but I don’t know anything about it.
Aside: I don’t know how much time regalloc takes compared to optimisation, linking, etc. but I wonder if there’s a noticeable difference in effort between x86_64 (where there are 16? registers, some with fixed purposes) and RISC-V (which has 32 registers with no fixed purpose, modulo ABI and compressed instructions).