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An FPGA development workflow for FPGA programming without any dirty proprietary software has been a long-sought-after goal for lots of us free-software hackers. Clifford Wolf has finally made it happen, just in the last few months! His Project IceStorm uses his reverse-engineering of the Lattice FPGA bitstream format to process the output from arachne-pnr into a valid bitstream, then program that bitstream onto the device.

Apparently he had to write his own Verilog synthesis tools too; dunno if Icarus Verilog wasn’t good enough, or if he just did that for fun.


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    In reading more about this project (I just heard of it!), I realize that I didn’t give Mathias Lasser proper credit for his part of Project IceStorm.

    Also! The FPGAs themselves are super cheap. Like US$1.53 at retail, although I think that one may not be supported by IceStorm yet. And the IceStorm and Arachne-pnr tools are super fast, with the subsecond compile times on this toy example that you would expect from decent software, while the Lattice tools are much slower. And IceStorm has successfully compiled a CPU and programmed it onto an FPGA, which you could consider either a proof of maturity of the software, or a waste of a perfectly good FPGA. Maybe this means the long-promised FPGA future of wonder can finally come to pass!

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      On reading further, he wrote Yosys (the Verilog synthesis tool) because nothing else out there, including Icarus Verilog, came close to what he needed. The Yosys manual says,

      Due to the author’s preference for Verilog over VHDL it was decided early on to go for Verilog instead of VHDL 2. So the existing FOSS Verilog synthesis tools were evaluated (see App. ??). The results of this evaluation are utterly devastating. Therefore a completely new Verilog synthesis tool was implemented and is recommended as basis for custom synthesis tools. This is the tool that is discussed in this document.

      Unfortunately I don’t know what App. ?? is. Nothing promising appears in the table of contents or bibliography. It seems to have been the deleted Appendix E. There’s a hint early on, though:

      Many FOSS tools that claim to be able to process Verilog in fact only support basic structural verilog and simple expressions.

      The Icarus Verilog FAQ has a more complete entry about this:

      Way back in the olden days, Icarus Verilog did indeed support synthesis, but that support has faded away. The last workable synthesis support was in versions 0.8. Starting in versions 0.9 to the current date, synthesis has been more or less dropped. It turns out that there is more than enough work to do catching up with the latest Verilog, SystemVerilog, Veriog-A/MS and VHDL to keep the current developers busy for the rest of our days. Combine that with a lack of real interest in workable synthesis in Icarus Verilog, and that FPGA vendors typically provide free synthesis tools, and the incentives are just not there.

      For an actively maintained open source Verilog synthesis tool, see yosys.

      Yosys itself looks very impressive indeed. An aside in appendix D:

      It might be worth noting, that SAT solvers are not particularly efficient at factorizing large numbers. But if a small factorization problem occurs as part of a larger circuit problem, the Yosys SAT solver is perfectly capable of solving it.