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      Kinda related but I’ve never been sure where to ask this: What is the purpose of a “monitor core” in RISC-V CPUs? I’ve never really gotten a good answer to this and googling for it only gets me to data sheets that tell me the monitor core exists, but not what it does.

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        As far as I could gather, they’re kind of like saner, more capable, and more importantly, user-programmable equivalents to e.g. Intel’s IME. The monitor core is a separate core that’s specifically built for deterministic, real-time execution. I’m only vaguely familiar with SiFive’s – theirs are actually pretty beefy cores, they don’t do floating point and don’t have an MMU but they’re basically as fast as the application cores. I think the original intent was to allow using it for sanity and performance monitoring, firmware implementation, system management and so on. I’m not sure what it’s used for IRL – given that it’s user-programmable, I guess a fair answer would be “anything that fits”.

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      RISC-V seems liked it’s still years away from being a common platform. The available hardware is mostly slower than similarly priced competition. The software support is lacking due to the options for hardware.

      I appreciate the enthusiasts and companies trying to move it forward, it just feels like a tech that’s on the rolling 3-5 years away window. Who knows, maybe Intel can change that, but they have competing priorities.

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        Remember, most CPUs aren’t your laptop or phone or desktop’s main CPU. Most CPUs are things like the disk controller in your hard drives, the CPU in your LTE modem, the little CPU in your power bank’s USB-C PD chip, etc. Areas where performance doesn’t matter, power consumption doesn’t really matter, but volume price is vital.

        In this area, any ISA will do the job, software support isn’t as much of an issue, and not having to pay ARM for a license for every chip sold is a pretty big advantage.

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          That’s a good point; I hadn’t considered the license fees. But I hear you can get ARM CPUs for quite literally pennies today, so the savings may not be too significant?

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            The license fees are often not the problem with Arm, the terms are:

            • You can’t add instructions for your workload (I think the newer M-profile licenses do allow this)
            • You can’t remove things to save area. With RISC-V, even integer multiplication is optional and you can subset bellow the standard if you’re willing to pay the toolchain costs.
            • You can’t sublicense. If you are building some IP block that needs a controller core, your customers will need to license directly from Arm.
            • Most Arm licenses are bespoke and tied to specific cores. It can take years to get a new license. Extending a license to new cores is easier but not automatic (not sure if this has improved, I flagged it as a reason they were going the haemorrhage business a few years ago). There are some off-the-shelf licenses for the smallest M-profile cores.

            Arm has some great tech but they really need to bring in some more competent people on the business side.

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            The savings aren’t always significant but the licensing terms are pretty complicated (and there have been some rumours that it might get even weirder in 2023). They change rather often so a bunch of this may be out of date but a few years back it was pretty tight. There were multiple license types, all of which came with some restrictions about what changes you could make to the IP you’d licensed and how you could extend them or integrate them in your design, on what designs you could use them in after licensing them and so on. It’s not so much a problem of licensing fees, or at least not just a problem of licensing fees, as it’s a problem of what you can do.

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        Unlike the standard “3-5 years away” riscv can be used for practical applications now, though. It’s not gonna rival a Ryzen or an M1, but neither does anything else and it’s not really meant to.

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          It’s not gonna rival a Ryzen or an M1, but neither does anything else and it’s not really meant to.

          There’s Ascalon, RISC-V core from Tenstorrent (CEO: Jim Keller), design lead by the same person that led M1.

          It currently outperforms projected Zen5, at lower power. Both Zen5 and Ascalon will launch in 2024.

          At that point, this perceived gap will favor of RISC-V, and from there the old ISAs will be left in the dust.

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        I appreciate the enthusiasts and companies trying to move it forward, it just feels like a tech that’s on the rolling 3-5 years away window.

        Doesn’t that mean it’s the best time for people that do actually care about the CPU architecture? Compared to end users, which mostly care about price, power consumption, etc., but not really about the architecture itself. I’d also assume this is the time where you don’t have to deal with overly much complexity and “baggage” (deprecated, historical stuff) yet.

        Learning and porting to new architectures is fun to some people. When an architecture is widely used I assume a lot of work that is left is probably boring, which I think is when people start to build toy OSs.

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      It would be nice to list the extensions that these come with. For example, the T-Head cores have a bunch of non-standard extensions that fix the worst flaws in the core ISA.

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        It certainly would! I’ve grabbed information on extensions where it’s readily available (and prioritised doing so for standard extensions). I can of course point to https://github.com/T-head-Semi/thead-extension-spec - but I’d ideally find a source which confirmed which SoCs with T-Head cores implement which of these extensions (or perhaps the whole set implemented by everything since the Allwinner D1?).

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      A number of RISC-V chips are available that are intended as flash drive or hard drive controllers. You probably already have a few! But they’re not meant for general purpose applications.