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    Good he found out it’s not a new idea and one of the papers.

    https://www.cs.columbia.edu/~angelos/Papers/instructionrandomization.pdf

    Edwin Barrantes also did years of work in this area like this:

    https://www.cs.unm.edu/~forrest/publications/rise-tissec.pdf

    My addition was doing it at the microcode level w/ 64-bit instructions so it could be set like a key. I don’t know hardware design, though, so I can’t tell you if there’s 1-2 cycle way to go from 64-bit input to a specific set of values. As in, is this implementable without negatively impacting the performance of a 1-3GHz chip? If so, you could have different microcode and assemblers per system. I looked into doing it with NISC architecture as well for stuff that runs on FPGA’s but again over my head.