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      Thanks for the links! Some of those are new to me.

      Mostly to learn new tricks (and for fun). I also wanted a simple way to generate state machines which are tedious to code in Verilog without the complexity of adding a processor to my designs.

      Clearly everything FPGA-related I do will be dominated by the FPGA research group at UofT. I also wrote arachne-pnr, the place-and-route engine used in IceStorm, the open-source toolchain for the Lattice iCE40 FPGAs. Clifford Wolf has started reverse-engineering the Xilinx 7-Series bitstream format (!) and plans to switch to VPR: https://twitter.com/oe1cxw/status/782257812114116608

      Synflow compiles Cx, its as far as I can tell is closed source.

      There’s also Xilinx’s High Level Synthesis (HLS) tool: https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html

      Wikipedia also has a list of C to HDL tools: https://en.wikipedia.org/wiki/C_to_HDL

      Surprising how much abandonware there is in this space.

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        Good work on the IceStorm stuff. Almost nobody doing FOSS EDA. Keep at it esp improving QFlow if possible.

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      Nice! I have also come across:

      Migen: Python to hdl

      Clash: Haskell to hdl

      I’m in the market for tools that understand both verilog and a higher language. As in, be able to parse verilog and provide an API to its AST, and at the same time generate code from a higher level language down to verilog. I have tinkered a little bit with iverilog’s api.