1. 8

  2. 0

    Undocumented opcodes? Please call them bugs. Anything outside the documented ISA should be an illegal instruction exception. If it’s not documented and it doesn’t cause an illegal instruction exception, it is a bug.

    This kind of thing is a major factor of x86 and derivatives making me sick. It is good RISC-V is taking off.

    1. 4

      To be fair these aren’t special to x86 — The undocumented/illegal instructions in 6510 NMOS CPUs are (relatively) well-known, and they aren’t alone in this, at all.

      And RISC-V doesn’t seem to be free from this either: while anyone can implement the spec freely, and some implementations are also freely available, it’s still incredibly hard to figure out what the actual hardware could be doing.

      1. 5

        I strongly bet most RISC-V implementations will end up being undocumented and put into deep embedded microcontroller scenarios. That’s where the money is (including the money that doesn’t want to give ARM money), and where almost all RISC-V interest is coming from.

        1. 2

          Yes, these bugs aren’t limited to x86, but x86 is a currently wide-deployed architecture that suffers from this problem. x86 is extremely complex, full of historical baggage.

          RISC-V implementations can indeed have undocumented instructions, but due to the extensible instruction space, this is less likely.

          I also do honestly expect most hardware to use the royalty-free OSHW cores, as they are very good. These are unlikely to have undocumented instructions, due to their open nature.