1. 13

  2. 2

    From the SERV user manual:

    SERV is a bit-serial CPU which means that the internal datapath is one bit wide.

    1. 2

      This is pretty amazing! The CPU core, admittedly without register file, takes less logic than many of my simple cores that perform much more mundane tasks.

      The presented applications, i.e. deeply embedded CPUs are also intriguing. A difference to most other deeply embedded processors is that RISC-V is a pretty generous architecture compared to e.g. an 8051 or a TMS1000, with many and wide registers. I am not sure, though, that the benefits can be upheld when looking at the processor paired with a memory, I/O and program storage.

      Nevertheless, a really cool project.

      1. 2

        Yes; to put a number to it, the first linked introductory video shows claims to implement the core on an Xilinx Artix 7 for 130 LUTs plus 206 Flip-Flops, plus memory (but the register file can be stored in the same block RAM holding code and data memory.)

        1. 2

          Thanks for pointing out that the code/data memory and the register file can be colocated. This is certainly attractive to keep the whole system resource usage down.

          I just realized that the external register file, especially if done with block RAM, lends itself to implement hardware supported threads or something similar to hyperthreading. By changing a base pointer into the RAM, the CPU can have multiple register files, with one of them being active at any given time.

          1. 2

            Many of the applications for a CPU like this don’t need any state outside of the CPU registers – especially as RISC-V lets you do multiple levels of subroutine call without touching RAM if you manually allocate different registers and a different return address register for each function (which means programming in asm not C). A lot of 8051 / PIC / AVR have been sold without any RAM (or with RAM == memory mapped registers)