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    This blog post seems to be only a fragment of this article: https://meribold.github.io/assets/cache-paper.pdf

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      In practice, a currently representative x86 cache hierarchy consists of: […] Often a unified L3 cache of 2 to 16 MiB shared between all cores.

      Note that this isn’t true for AMD’s current Ryzen processors. On these processors, there are two 8 MiB L3 caches shared between half the cores. If an application has threads on both caches that try to share data, it will run a lot slower than with everything on the same cache.