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    Their site used to have good descriptions, the software to do this, and samples. It was recently “excluded” from Wayback Machine. People been doing that a lot past two years. Assholes. Anyway, I found some non-paywalled papers describing NISC in a number of ways:

    NISC Technology and Preliminary Results (2005) http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.218.5994&rank=4

    Communication Design for NISC (2005) http://www.cecs.uci.edu/technical_report/TR05-09.pdf

    Use of NISC for Acceleration in Wishbone-based Systems (2008) http://www.fer.unizg.hr/_download/repository/APPOES_TR_11_14_08.pdf

    For anyone with paywall access, the 2007 Dissertation is available here:

    https://dl.acm.org/citation.cfm?id=1354283

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      So… an FPGA?

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        It’s more about how you do the hardware design than what it’s done on. Traditionally, people have to do a custom, HW design to solve a problem. That takes a lot of time and is very different from software apps. Then, people started accelerating specific functions on FPGA’s with regular stuff done in software. Then, to help avoid HW expertise on those the high-level synthesis tools were born that try to generate an entire piece of hardware from high-level code. The lack of flexibility or efficiencies of that led people to look for new compromises.

        One was NISC. They start with some hardware blocks that perform useful functions that might also be connected to CPU’s. We’re actually seeing that in SoC’s today. The CPU’s usually have a fixed set of instructions that use the blocks in a specific way. The accelerators often similarly have fixed API if they don’t synthesize on demand to FPGA’s. So, NISC takes it further by eliminating those fixed functions, analyzing your algorithm to see its control/data needs, and generating hopefully-optimal control and data paths for it leveraging the blocks it has. You can also selectively do custom blocks if synthesis isn’t good enough on something. Your necessary HW expertise or labor is lowered in many cases since the synthesis might be enough of a boost. The result can go on a FPGA, S-ASIC, ASIC, whatever.

        That’s at least what I got out of reading the original site before it disappeared.

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          Thanks for the response. I designed a MIPS processor (RISC) in Verilog last year, I’d never heard of NISC until now though. The part I’m stuck on is how one would write a program to run on a NISC-y processor. Does it truly have no instructions? How else would I tell it “add these two values together”? Maybe I’m being too literal here…

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            Instructions are just operations on controland data paths of the hardware. This is like a HLS tool for programming code that produces custom control/data for your algorithm. It customizes the instructions and their implementation to you algorithm’s requirements.

            For something similar, look up Tensilica’s Extensa CPU’s. They make custom CPU’s plus toolchains to go with them.