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    The prices are still hair-raising high. Yet I might actually go and buy the riscv arduino board this year. Simply because this modular instruction set architecture is gorgeous. It’s almost more pleasure to use than many programming languages today and by the looks of it should be the nicest compiler target to support.

    The RV32I base instruction set allows you to write position independent code so easily that there’s really no point to do anything else. Also the set is really spartan, minimal and the semantics of each instruction are obvious. Summarizing that set you get:

    1. Load long address / PC relative address in.
    2. Jump and link register / indirect jumps.
    3. Integer comparison & conditional jump.
    4. Load/store instructions (byte, short, word). Address, integer offset, destination register.
    5. Addition instruction that doubles as move.
    6. Set register 1 if register less than the immediate value.
    7. Bunch of arithmetic (add/sub/shifts/xor/or/and)
    8. Fences
    9. system calls
    10. debugger break instructions.
    11. System status registers, for example real-time-clock can be accessed from there.

    The jump-and-link does both the jumps and the calls. It recognizes which one you do by conventions. eg. register 1 is used as a link register on calls and you return by using the link register.

    The nicest thing is that there’s no integer flag registers with operational semantics undocumented in most of the documentation specs. The BEQ/BNE/BLT/BGE/BLTU/BGEU take two registers to compare and if the condition fullfills it will jump.

    The instruction set seems to have bit of forward-thinking done in. It’s got holes so that you can get yourself 16-bit, 64-bit or 128-bit instruction lengths in the future, while not having them collide with the current 32-bit instructions. It looks like they got a way to list features used by the programs in the program headers of ELF-binaries, so this modularity -thing should work rather well in practice.

    I’ll be sending some blog posts about this soon. I have some stuff done but I want to add more stuff in first.

    People really underestimate what kind of a cluster fuck x86_64 is to support, and how the ARM isn’t going much behind in being a similar piece of ***t.

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      ARM isn’t going much behind in being a similar piece of ***t

      Really? When AArch64 was introduced, it was described as “the best target a compiler could hope for” :) Do you know of any specific bad parts?

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        Do you know of any specific bad parts?

        The NDA’s and royalties. ;)

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          That’s for chip makers. Programmers / compiler authors don’t have that on any architecture :D

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            The embedded people, esp doing driver development, sometimes complain about that stuff. They say they’d be able to make good drivers more quickly if they could get more details on hardware operation. I speculate open HDL might not have that problem. However, it’s possible a lot of what’s in this machine might be closed if they had to use 3rd-party I.P. for practical reasons. So, this is more a long-term benefit for peripheral I.P. done openly than RISC-V itself.

            On RISC-V, detailed access to chip internals will help us review it more quickly for security problems like side channels. One can also fuzz the implementation by testing against the RTL models. Lots of possibilities.

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          Was thinking of it a while. Technically compared to ARM, Risc-v is similar except that ARM does some things bit differently. I think most of the pain with ARM is related to Raspberry Pi and comes from the rest of stuff around the ISA. You got two, or three? different platforms that are incompatible. The binary blob stuff is just atrocious. Bootup forced through FAT filesystem was annoying. The main documentation you hit when searching is very quiet about how the stuff is encoded. ARM is also least accessible despite that it’s apparently ubiquitous. They don’t want that hobbyists tinker the stuff? Okay. Lets not tinker.

          On RISC-V I basically were thrown in. The toolchain was easy to compile, setup and the simulator was available.

          Of course a RISC-V could also become a landfill generator if it’s being treated just as an ARM-drop-in replacement.

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            Oh, the Raspberry Pi is absolute trash on the low level. Worse than Broadcom’s extremely weird boot process, that chip uses a custom Broadcom interrupt controller instead of the ARM GIC, which literally every other chip uses.

            With Allwinner and Rockchip based SBCs, you just flash mainline U-Boot onto an onboard SPI flash and do whatever you want (I netboot diskless FreeBSD on them). Allwinner is not friendly (everything was reverse engineered), but Rockchip provides very detailed manuals and contributes drivers to mainline Linux.

            But neither the RPi nor the better SBCs have anything to do with the wider ARM ecosystem of Real Computers™. Server grade machines and Windows-on-ARM laptops support UEFI+ACPI, everything is standardized and “boring” i.e. works just like x86. Even normal PC graphics cards usually work because the UEFI has QEMU inside it to emulate the x86 code that’s flashed on the graphics card and provides a display output driver for the firmware. And on some boards the firmware is FOSS!

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        What’s the advantage to POWER9 PC?

        POWER9 is faster and more expandable, while having similar price.

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          Some people just specifically want an architecture for subjective reasons. I guess RISC-V being a new, cool™ and royalty-free ISA is a factor in this :) The perception of IBM as the uncool enterprise monster too, to a lesser extent.

          tbh, the Raptor Talos line and the SiFive Unleashed (with the expansion board especially) are both incredibly expensive. The only non-amd64 PC platform I’m considering is the Marvell MACCHIATObin.

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            Blackbird (also from Raptor) is much cheaper, though.

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              Oh, right, the expansion board for the Unleashed is $1999, so we’re looking at $3000 vs $1200 (4-core bundle). I was thinking $2000 (incorrectly assuming the expansion is also $1000) vs $1500 (8-core Blackbird bundle).

              Meanwhile the Macchiatobin is $269 :)

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                True, but Blackbird is also much more powerful :)

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            In my opinion they are not comparable. It is like looking at ARM and asking, whats the advantage over X64? Well, they have different purposes. POWER9 is targeted at a different set of tasks than RISC-V which is flexible to be used in spaces where MCUs like AVR, PIC and ARM dominate while still scaling up to territories currently covered by ARM and still up to X86 stuff. So it is a very flexible ISA. So far we’ve seen real world boards mostly catering to the MCU space such as the HiFive1 (https://www.sifive.com/boards/hifive1).

            POWER9 is a whole different thing, it scales from WE’RE A FRICKING SERVER to WE’RE A LARGE FRICKING SERVER!!! Yes, you can use it as a Desktop, you can use it fo scientific computing, your build farm, whatever requires a ton of computing but you’d not put a POWER9 as a microcontroller for a router, nor would you build IoT stuff out of it. RISC-V might be a very flexible architecture that permeates a large part of our industry soon, people using the current crop of development boards are just getting ready for when it happens.

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              You’re comparing RISC-V (architecture, which may be available in different sizes and prices) to one CPU. If you compare just RISC-V to POWER (so architecture to architecture), you can see that POWER is already available in embedded markets (of course it’s not a free as in freedom architecture, but this wasn’t my point).. But I wasn’t comparing POWER9 to the whole RISC-V architecture, only Unleashed to Talos / Blackbird (which is similar pricewise, but not so in other terms).