A more recent Haskell hardware design tool is Clash. It takes a more directly functional approach than Bluespec or Chisel, which I’m sure hardware folks will tend to dislike but suits me just fine. Meanwhile, Verilog continues to be the computing industry’s most successful practical joke.
My guess is the impetus to fix this mess will come when people wisen up to the fact that they can’t count on free speed bumps from Intel every two years. That’ll cause both GPUs and FPGAs to get more popular in general use, which will encourage folks to develop less braindead tooling for both.
It’s also worth emphasizing that using any of Clash/Chisel/Bluespec/etc plus an FPGA significantly cuts down on the traditionally-horrible testing cycles of hardware design. FPGA tooling is still remarkably bad, but projects like Icestorm are working to fix that, for certain chips at least.
I remember having to use Verilog in my computer architecture courses. Truly frustrating stuff. In Advanced Architecture we were supposed to implement Tomasulo’s algorithm in Verilog, working in groups of two. Of course, the class never taught Verilog, because you were supposed to have learned it in a previous course. And of course we’d all taken said previous course at the same time, with a professor who didn’t bother to teach Verilog. Let me tell you, trying to implement Tomasulo’s algorithm (a hardware design for which there appears to be only one diagram available anywhere) in Verilog, with no knowledge beforehand of how Verilog actually works, in a 10-week quarter in which you’re working and taking 17 units, is not an easy feat. I will be happy never to use Verilog again.
Been watching the hardware design guys for awhile now….
Hardware design is just like software design….. Nothing to it.
Except in hardware design the basic primitives were all designed by satan.
Real time reposting of Dan Luu’s blog with a three year delay? I could live with that.
A more recent Haskell hardware design tool is Clash. It takes a more directly functional approach than Bluespec or Chisel, which I’m sure hardware folks will tend to dislike but suits me just fine. Meanwhile, Verilog continues to be the computing industry’s most successful practical joke.
My guess is the impetus to fix this mess will come when people wisen up to the fact that they can’t count on free speed bumps from Intel every two years. That’ll cause both GPUs and FPGAs to get more popular in general use, which will encourage folks to develop less braindead tooling for both.
It’s also worth emphasizing that using any of Clash/Chisel/Bluespec/etc plus an FPGA significantly cuts down on the traditionally-horrible testing cycles of hardware design. FPGA tooling is still remarkably bad, but projects like Icestorm are working to fix that, for certain chips at least.
I remember having to use Verilog in my computer architecture courses. Truly frustrating stuff. In Advanced Architecture we were supposed to implement Tomasulo’s algorithm in Verilog, working in groups of two. Of course, the class never taught Verilog, because you were supposed to have learned it in a previous course. And of course we’d all taken said previous course at the same time, with a professor who didn’t bother to teach Verilog. Let me tell you, trying to implement Tomasulo’s algorithm (a hardware design for which there appears to be only one diagram available anywhere) in Verilog, with no knowledge beforehand of how Verilog actually works, in a 10-week quarter in which you’re working and taking 17 units, is not an easy feat. I will be happy never to use Verilog again.