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    Sorry for the HN link, but a while back I wrote about how the x86 loop instruction was intentionally slowed down because of windows compatibility: https://news.ycombinator.com/item?id=2601014. Unfortunately all the links are broken now :/

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      I was wondering when Andrew’s thesis would show up here. If you like this, check out our recently published tech report on RocketChip, our open-source RISC-V SoC generator.

      http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html

      I’m a Ph.D. student at UC Berkeley in the computer architecture lab. I worked with Andrew before he graduated and will be interning at his new company, SiFive, this summer. Happy to answer any questions about RISC-V or RocketChip.