As it stands the POWER ISA has a decently comprehensive ecosystem, with a reasonably wide ranging instruction set. I’m curious as to whether this includes some of the PowerPC stuff still used in embedded systems or whether that stuff is covered by FreeScale (Motorola) IP.
I do think designing a POWER CPU would definitely be a fun exploratory project now that all of the stuff is openly available though.
My thinking is this is just OpenPOWER (i.e., POWER8 and up). But I’d be delighted to be wrong.
You mean cores or instructions? I haven’t been in PowerPC in over a decade, but I remember PowerPC being a subset of POWER in terms of ISA.
In the 32-bit era, yes. However, 64-bit PowerPC and Power ISA are pretty much synonymous. The classic example is the G5, which is truly a member of the PowerPC family (“PowerPC 970”), but is a 64-bit processor basically consisting of a POWER4 with an AltiVec unit bolted on. You can see this in the instructions, for example (no mcrxr, no dcba, 128-byte cache line behaviour with dcbz, exactly the same as this POWER9).
That makes a ton of sense. Thanks for the history lesson!
Instructions. AFAIR the embedded versions of PowerPC add a bunch of instructions and other architectural features to support hardware things, but you might be right.
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weird dupe, deleting.
Still waiting for that POWER9 based laptop with classic 7-row ThinkPad keyboard …
it’s 90W - it’s going to be one of those incredibly thick gamer laptops at best
What prevents them from making a one with 2 cores and SMT4 at 25W envelope? :)
The market for it. (Also, the 90W figure is for the 4-core part that pretty only exists as chaff that RCS uses and IBM otherwise wouldn’t. POWER9 is designed for 4-8 thread clumps - IBM sells single-core/thread models, but those use firmware DRM to be restricted)
Which ones are those?
Servers like the S812 Mini. The AIX configuration has more cores, but the i configuration is limited to a single one.
Oh, yes. IBM i definitely plays by different rules.
The limiting factor for the 4cores aren’t the cores itself, but all the peripheries like the PCIe host bridges, the core interconnect, the onchip accelerators, the MMU etc.