There are some interesting points made here and a lot of them are definitely cases of lessons learned the hard way over many generations of CPU architecture. I do take exception to some of his points though. The essential attribute of RISC architectures is that they’re designed to make the CPU’s instruction unit as simple as possible, so when he says:
The x86 system for storing 32-bit/64-bit immediates is much nicer. They just follow the instruction, which is possible because the instruction length is variable. Variable-length instructions are not usually seen in RISC…
What he’s actually saying is that as a programmer he prefers a more complex instruction coding because it makes his life easier. I can understand that but variable length instructions are pretty much the antithesis of RISC. What he’s really saying here is that he likes CISC. Which is fine and very understandable from a programmer point of view, but not an argument that there’s something wrong with these RISC architectures since their aim is to reduce IU complexity, not to make the programmer’s life easier.
There are some interesting points made here and a lot of them are definitely cases of lessons learned the hard way over many generations of CPU architecture. I do take exception to some of his points though. The essential attribute of RISC architectures is that they’re designed to make the CPU’s instruction unit as simple as possible, so when he says:
What he’s actually saying is that as a programmer he prefers a more complex instruction coding because it makes his life easier. I can understand that but variable length instructions are pretty much the antithesis of RISC. What he’s really saying here is that he likes CISC. Which is fine and very understandable from a programmer point of view, but not an argument that there’s something wrong with these RISC architectures since their aim is to reduce IU complexity, not to make the programmer’s life easier.